The present invention relates to a power converter and especially to a balanced current converter with multiple pulse width modulated channels.
Since the power consumption of computer central processing units (CPU) is increasing, direct current (DC) converters need to supply more than 60 amps of current for computer operation. Consequently, a multi-channel structure converter provides a more economical performance than a single channel converter. Of the multi-channel converters, a smaller and cheaper filter capacitor may be chosen for the multi-channel pulse width modulated (PWM) converter having a current ripple scattering effect. Therefore, most of the parallel multi-channel converters employ the structure of the PWM converter channels.
A multi-channel converter connects in parallel a plurality of pulse width modulated channels with the same output voltage to provide a higher output current. There is often a voltage difference between the channels supplying the same load. The difference between the channels may occur in one or several channels providing a comparatively higher current. In particular, some types of converters, such as synchronous rectified converters, have the ability to sink as well as source output current. In these converters, a great current may flow from one channel to another. This phenomenon can lead to excessive power dissipation, at which point these channels bear the highest power load. Thereafter, the supplying ability of working components in every channel must be increased and the load that the converter supplies must be limited to below the combined full load capability of the individual channel. Therefore, the converter cost may increase and the life span thereof may be reduced for only a few channels working in the high temperature. A converter with the capability to share and balance the load current may be the better choice. Every channel provides the same current; that is to say, every channel bears the same load and has almost the same life span. The life span and cost problems are solved by sharing and balancing the load current.
U.S. Pat. No. 6,285,571 discloses a converter with a plurality of converter channels. In the converter, all channels measure the average output voltage thereof in front of the position of the inductor and then compare the average output voltages and adjust their PWM duty cycle to reduce the deviation average output voltages between channels. Therefore, the converter may achieve current sharing with comparison of the average output voltages of the channels. The method may reduce the deviation average output voltage of every channel but the inductance of the inductors is reduced when the power switch on-off frequency is increased. The equivalent resistance of the inductor constructed by the lower inductance is also reduced. The lower resistance causes a higher current imbalance when there is a small offset voltage between the channels. For example, an offset voltage 15 mV divided by the equivalent resistance of the inductor 3 milliohm equals a 5 amps current. Therefore, the huge current flows from the higher voltage channels into the lower voltage channels.
Another U.S. Pat. No. 6,278,263 discloses a multi-phase DC/DC converter including a plurality of converter channels. Each converter channel is configured for generating a converter channel current and for adjusting the converter channel current in response to a channel deviation current signal representative of a comparison of the channel current signal to an average current signal and an error signal representative of a comparison of the converter output voltage to a reference voltage. The average current signal is representative of an overall average current for the converter channels. Therefore, the pulse width modulator controls the duty cycle thereof to provide a sharing and balancing output current. FIG. 1 is a sketch of a multi-phase converter with balanced currents. The current sensor 110 detects the signal, V1SEN1, the output current of the converter channel. The summing circuit 102 sums V1SEN1, V1SEN2, and V1SEN3 and then, the scaling circuit 103 scales (divides by 3) the sum of V1SEN1, V1SEN2, and V1SEN3 to obtain an average output current signal of the converter. Every output current signal V1SEN1, V1SEN2, and V1SEN3 is compared with the average output current signal. Depicting one converter channel, the subtraction circuit 104 subtracts the average output current signal from the V1SEN1 to obtain a bias signal. The bias signal goes through the compensation circuit 105 to filter and gain the bias signal, and then arrives at the subtraction circuit 106. The subtraction circuit 106 compares the filtered and enhanced signal with a deviation signal generated by the error amplifier (E/A) 101 and generates a modified deviation signal wherein the error amplifier 101 compares the VREF and the output voltage of the converter to generate the deviation signal. Therefore, the subtraction circuit 106 outputs the modified deviation signal to the pulse width modulator 107. With the ramp input and the modified deviation signal from the subtraction circuit 106, the pulse width modulator 107 controls the duty cycle of the power switch 108 to provide a pulse power output. The inductor 109 and the capacitor 112 filter the pulse power output to form a direct current output to the load 111. As in the above description, the converters sense current signals of all converter channels and then adjust every output current of the converter channels based on the bias signal compared with the average current signal and the current signal of every converter channel. There are still some problems in the converters. One is that the control circuit of the converter is too complex and another is that the average circuit must be modified if the quantity of the converter channels is changed.
According to the above description, the converter that simplifies the control circuits thereof and shares the load with the all-working channels with balanced current is needed for the multi-channel PWM converter.
The present invention provides a balanced current converter with multiple pulse width modulated channels.
The invention comprises a balanced current converter comprising a converter output, an error amplifier, a main converter channel and at least one parallel converter channel. The converter output provides a power output and an average output voltage signal. The error amplifier inputs the reference voltage signal and the average output voltage signal, and compares them to generate an error signal. The main converter channel couples within the converter output and the error amplifier and outputs the main channel current signal and the main channel power output according to the error signal. The parallel converter channel couples within the converter output and the error amplifier, and connects with the main converter channel to obtain the main channel current signal. The parallel converter channel compares the main channel current signal and the respective parallel channel current signal to generate the first deviation signal, and then the parallel converter channel compares the first deviation signal and the error signal to generate a second deviation signal. The parallel converter channel provides a respective parallel channel power output and measures the respective parallel channel power output to feed back the respective parallel channel current signal, wherein the power output includes the main channel power output and the respective parallel channel power output.
The main converter channel comprises a pulse width modulator inputting the error signal and outputting a pulse width modulated signal, a power switch inputting the pulse width modulated signal, adjusting the duty cycle thereof and then outputting a pulse power based on the pulse width modulated signal, a filter, an inductor and a capacitor for filtering the pulse power to the main channel power output, and a channel current sense circuit, a resistor and a differential amplifier for detecting the main channel power output and generating the main channel current signal. The channel current sense circuit may utilize a precision resistor or a turn-on resistor of the power switch to measure a voltage deviation between two ends of the resistor.
The parallel converter channel comprises a second subtraction circuit outputting the second deviation signal, a pulse width modulator inputting the second deviation signal and generating a pulse width modulated signal, a power switch inputting the pulse width modulated signal and outputting a pulse power, a filter, an inductor and a capacitor filtering the pulse power to the respective parallel channel power output, a first subtraction circuit inputting the main channel current signal and the respective parallel channel current signal and outputting the first deviation signal, and a channel current sense circuit, a resistor and a differential amplifier detecting the respective parallel channel power output and generating the respective parallel channel current signal. The second subtraction circuit inputs the first deviation signal and the error signal and generates the second deviation signal. The parallel converter channel further comprises a compensation circuit between the first subtraction circuit and the second subtraction circuit to filter and gain the signal. Additionally, the parallel converter channel can be turned on and turned off.
In another aspect, the invention provides a balanced current converter which comprises a converter output providing a power output and an average output voltage signal, an error amplifier comparing the reference voltage signal and the average output voltage signal to generate an error signal, and a plurality of converter channels in parallel coupled within the converter output and the error amplifier. Each of the plurality of converter channels comprises a pulse width modulator to adjust a respective power output of the converter channel. The converter may select one of the converter channels as a main converter channel with the highest respective power output of the converter channels, and select the other converter channels as a plurality of parallel converter channel.